1. Field of the Invention
The present invention relates to a power amplifier provided with a power distribution circuit which distributes an input signal into a plurality of signals and outputs the signals, a plurality of amplification circuits which amplify the respective signals outputted from the power distribution circuit and a power combining circuit which combines the respective signals outputted from the plurality of amplification circuits and outputs the combined signal, and more particularly, to a power amplifier which is capable of reducing the chip size and advantageous from the standpoint of stable production.
2. Background Art
FIG. 13 is a circuit diagram showing a conventional power amplifier. This power amplifier is constructed of a power distribution circuit 11 which distributes an input signal into four signals and outputs the signals, four amplification circuits 12 such as FETs and HBTs which amplify the respective signals outputted from the power distribution circuit 11 and a power combining circuit 13 which combines the respective signals outputted from the four amplification circuits 12 and outputs the combined signal. Furthermore, matching circuits 14, 15 are disposed between an input terminal and the power distribution circuit 11 and between an output terminal and the power combining circuit 13 respectively. High output can be obtained by causing a plurality of amplification circuits to operate in parallel in this way (e.g., see Japanese Patent Laid-Open No. 11-355015).
In such a power amplifier, a closed loop is formed because a power distribution circuit and a power combining circuit are used. When there are variations in the amplification circuits and circuit elements, loop oscillation occurs in this closed loop at a specific frequency, which causes the power amplifier to become unstable. Therefore, the conventional power amplifier disposes stabilization circuits 16 in series between the plurality of amplification circuits 12 and power distribution circuits 11 respectively to prevent loop oscillation. This allows stability to be improved with stability factor K set to 1 or above in the close vicinity of the amplification circuits, and thereby makes it easier to suppress loop oscillation produced in the power combining power distribution circuits and facilitates the design of the whole circuit.
However, in the conventional power amplifier, a stabilization circuit needs to be provided for each of the plurality of amplification circuits, which increases the chip size and increases the cost. When, for example, a circuit made up of a resistor 17 and capacitor 18 connected in parallel is used as the stabilization circuit, the size in a direction perpendicular to the input/output direction is determined by the resistor 17 and capacitor 18. Furthermore, when an element requiring bias application is used in the stabilization circuit, it is necessary to increase the size in the input/output direction for leading out bias lines from the stabilization circuit disposed inside. Moreover, adopting a complicated structure to realize a multi-function stabilization circuit increases the area occupied by the stabilization circuit, and therefore it is difficult to realize such a structure when priority is given to a cost reduction. Furthermore, the conventional power amplifier includes numerous elements making up the stabilization circuit such as capacitors and resistors, which makes the amplifier more susceptible to variations in the respective elements and this is disadvantageous from the standpoint of stable production.